There are known conventional hetero junction field effect transistors (HJFETs) found in Non-Patent Document 1 and Patent Document 1.
FIG. 15 is a sectional view showing a configuration of an HJFET described in Non-Patent Document 1.
The HJFET shown in FIG. 15 has a buffer layer 201, a channel layer 202 composed of gallium nitride (GaN), and a carrier supply layer 203 composed of aluminum gallium nitride (AlGaN) stacked in this order on a sapphire substrate 200.
In the HJFET, a two-dimensional electron gas 204 is formed in the channel layer 202 in the vicinity of the interface with the carrier supply layer 203, based on piezoelectric polarization effect ascribable to difference in the lattice constants between GaN and AlGaN, and based on an effect of spontaneous polarization.
On the carrier supply layer 203, there are formed a source electrode 205S and a drain electrode 205D while establishing ohmic contact therewith. A gate electrode 207 is formed on the AlGaN carrier supply layer 203 in a region fallen between the source electrode 205S and the drain electrode 205D, while establishing Schottky contact at the interface 203A with the carrier supply layer 203.
On the carrier supply layer 203 and the gate electrode 207, there is provided also a surface passivation film 208 composed of silicon nitride (SiN).
Alternatively, Patent Document 1 describes a normally-off HJFET having a channel layer composed of a non-doped GaN layer, and a barrier layer composed of AlGaN formed on, and brought into contact with, the channel layer. In order to realize the normally-off configuration of HJFET, which is intrinsically configured as normally-on, there is also described that a p-type semiconductor layer containing a p-type impurity is provided in the barrier layer under the gate electrode.                [Non-Patent Document 1] Y. Ando et al., Technical Digest of International Electron Device Meeting, p. 381, 2001        [Patent Document 1] Japanese Patent Application Publication No. 2004-273486        